| 000 -LEADER |
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| fixed length control field |
02389nam a2200253Ia 4500 |
| 005 - DATE AND TIME OF LATEST TRANSACTION |
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| control field |
20250819122049.0 |
| 008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION |
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| fixed length control field |
241121s9999 xx 000 0 und d |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER |
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| ISBN |
9788177589184 |
| 041 ## - LANGUAGE CODE |
|---|
| Language code of text/sound track or separate title |
eng |
| 082 ## - DEWEY DECIMAL CLASSIFICATION NUMBER |
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| Classification number |
621.392 PAL/V |
| 100 ## - MAIN ENTRY--AUTHOR NAME |
|---|
| Personal name |
Palnitkar, Samir |
| 245 #0 - TITLE STATEMENT |
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| Title |
Verilog HDL: a guide to digital design and synthesis (with CD) |
| 250 ## - EDITION STATEMENT |
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| Edition statement |
2nd ed. |
| 260 ## - PUBLICATION, DISTRIBUTION, ETC. (IMPRINT) |
|---|
| Name of publisher |
Pearson India |
| Place of publication |
Noida |
| Year of publication |
c2003 |
| 300 ## - PHYSICAL DESCRIPTION |
|---|
| Number of Pages |
490p.; 24cm. |
| Accompanying material |
CD-ROM |
| 500 ## - GENERAL NOTE |
|---|
| General note |
Table of Content<br/> 1 BASIC VERILOG TOPICS.<br/> 1.1 Overview of Digital Design with Verilog HDL.<br/> 1.2 Hierarchical Modeling Concepts.<br/> 1.3 Basic Concepts.<br/> 1.4 Modules and Ports.<br/> 1.5 Gate-Level Modeling.<br/> 1.6 Dataflow Modeling.<br/> 1.7 Behavioral Modeling.<br/> 1.8 Tasks and Functions.<br/> 1.9 Useful Modeling Techniques.<br/><br/> 2 ADVANCED VERILOG TOPICS.<br/> 2.1 Timing and Delays.<br/> 2.2 Switch Level Modeling.<br/> 2.3 User-Defined Primitives.<br/> 2.4 Programming Language Interface.<br/> 2.5 Logic Synthesis with Verilog HDL.<br/> 2.6 Advanced Verification Techniques.<br/> |
| 520 ## - SUMMARY, ETC. |
|---|
| Summary, etc |
Fully updated for the latest versions of Verilog HDL, this complete reference progresses logically from the most fundamental Verilog concepts to today's most advanced digital design techniques. Written for both experienced students and newcomers, it offers broad coverage of Verilog HDL from a practical design perspective. One step at a time, Samir Palnitkar introduces students to gate, dataflow (RTL), behavioral, and switch level modeling; presents the Programming Language Interface (PLI); describes leading logic synthesis methodologies; explains timing and delay simulation; and introduces many other essential techniques for creating tomorrows complex digital designs. Palnitkar offers a wealth of proven Verilog HDL modeling tips, and more than 300 fully-updated illustrations, examples, and exercises. Each chapter contains detailed learning objectives and convenient summaries. |
| 650 ## - SUBJECT ADDED ENTRY--TOPICAL TERM |
|---|
| Topical Term |
Computer engineering |
| 650 ## - SUBJECT ADDED ENTRY--TOPICAL TERM |
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| Topical Term |
System analysis and design |
| 650 ## - SUBJECT ADDED ENTRY--TOPICAL TERM |
|---|
| Topical Term |
Hardware description language (HDL) |
| 650 ## - SUBJECT ADDED ENTRY--TOPICAL TERM |
|---|
| Topical Term |
Verilog (Computer hardware description language) |
| 856 ## - ELECTRONIC LOCATION AND ACCESS |
|---|
| Uniform Resource Identifier |
https://www.pearsoned.co.in/web/books/9788177589184_Verilog-HDL_Samir-Palnitkar.aspx |
| 942 ## - ADDED ENTRY ELEMENTS (KOHA) |
|---|
| Koha item type |
Book |
