000 02389nam a2200253Ia 4500
999 _c3489
_d3489
005 20250819122049.0
008 241121s9999 xx 000 0 und d
020 _a9788177589184
041 _aeng
082 _a621.392 PAL/V
100 _aPalnitkar, Samir
_914360
245 0 _aVerilog HDL: a guide to digital design and synthesis (with CD)
250 _a2nd ed.
260 _bPearson India
_aNoida
_cc2003
300 _a490p.; 24cm.
_eCD-ROM
500 _aTable of Content 1 BASIC VERILOG TOPICS. 1.1 Overview of Digital Design with Verilog HDL. 1.2 Hierarchical Modeling Concepts. 1.3 Basic Concepts. 1.4 Modules and Ports. 1.5 Gate-Level Modeling. 1.6 Dataflow Modeling. 1.7 Behavioral Modeling. 1.8 Tasks and Functions. 1.9 Useful Modeling Techniques. 2 ADVANCED VERILOG TOPICS. 2.1 Timing and Delays. 2.2 Switch Level Modeling. 2.3 User-Defined Primitives. 2.4 Programming Language Interface. 2.5 Logic Synthesis with Verilog HDL. 2.6 Advanced Verification Techniques.
520 _aFully updated for the latest versions of Verilog HDL, this complete reference progresses logically from the most fundamental Verilog concepts to today's most advanced digital design techniques. Written for both experienced students and newcomers, it offers broad coverage of Verilog HDL from a practical design perspective. One step at a time, Samir Palnitkar introduces students to gate, dataflow (RTL), behavioral, and switch level modeling; presents the Programming Language Interface (PLI); describes leading logic synthesis methodologies; explains timing and delay simulation; and introduces many other essential techniques for creating tomorrows complex digital designs. Palnitkar offers a wealth of proven Verilog HDL modeling tips, and more than 300 fully-updated illustrations, examples, and exercises. Each chapter contains detailed learning objectives and convenient summaries.
650 _aComputer engineering
_94707
650 _aSystem analysis and design
_914361
650 _aHardware description language (HDL)
_914362
650 _aVerilog (Computer hardware description language)
_96283
856 _uhttps://www.pearsoned.co.in/web/books/9788177589184_Verilog-HDL_Samir-Palnitkar.aspx
942 _cBK