TY  - BOOK
AU  - Palnitkar, Samir 
TI  - Verilog HDL: a guide to digital design and synthesis (with CD)
SN  - 9788177589184
U1  - 621.392 PAL/V 
PY  - 2003///
CY  - Noida
PB  - Pearson India
KW  - Computer engineering
KW  - System analysis and design
KW  - Hardware description language (HDL)
KW  - Verilog (Computer hardware description language)
N1  - Table of Content
    1  BASIC VERILOG TOPICS.
        1.1  Overview of Digital Design with Verilog HDL.
        1.2  Hierarchical Modeling Concepts.
        1.3  Basic Concepts.
        1.4  Modules and Ports.
        1.5  Gate-Level Modeling.
        1.6  Dataflow Modeling.
        1.7  Behavioral Modeling.
        1.8  Tasks and Functions.
        1.9  Useful Modeling Techniques.

    2  ADVANCED VERILOG TOPICS.
        2.1  Timing and Delays.
        2.2  Switch Level Modeling.
        2.3  User-Defined Primitives.
        2.4  Programming Language Interface.
        2.5  Logic Synthesis with Verilog HDL.
        2.6  Advanced Verification Techniques

N2  - Fully updated for the latest versions of Verilog HDL, this complete reference progresses logically from the most fundamental Verilog concepts to today's most advanced digital design techniques. Written for both experienced students and newcomers, it offers broad coverage of Verilog HDL from a practical design perspective. One step at a time, Samir Palnitkar introduces students to gate, dataflow (RTL), behavioral, and switch level modeling; presents the Programming Language Interface (PLI); describes leading logic synthesis methodologies; explains timing and delay simulation; and introduces many other essential techniques for creating tomorrows complex digital designs. Palnitkar offers a wealth of proven Verilog HDL modeling tips, and more than 300 fully-updated illustrations, examples, and exercises. Each chapter contains detailed learning objectives and convenient summaries
UR  - https://www.pearsoned.co.in/web/books/9788177589184_Verilog-HDL_Samir-Palnitkar.aspx
ER  -